1. FIELD OF THE INVENTION
The present invention relates to forward error correcting transmitter and receiver used for digital transmission such as multiphase PSK (Phase Shift Keying) and multi-value QAM (Quadrature Amplitude Modulation).
2. DESCRIPTION OF PRIOR ART
Along with the recent progress of band compression technology of image signals through digital signal processing, transmission of digital data is now being used not only in the communications area but also widely used in the broadcasting area, and a forward error correcting apparatus for digital transmission such as QPSK (Quadrature Phase Shift Keying) and 16QAM has become essential technology.
The conventional forward error corrector is composed of a transmitter for transmitting digital signals and a receiver for receiving thus transmitted digital signals.
The transmitter comprises a convolution encoder which converts an input digital signal to be transmitted into a forward error corrected code, an interleaver circuit which changes a sequence of output data within each predetermined block length, and a digital modulator which modulates an output of the interleaver circuit.
The receiver comprises a digital demodulator which demodulates a received digital signal, a block phase control circuit which controls a block partition of the demodulated digital signal, a deinterleaver circuit which releases interleaving effected on the transmitting side, and a Viterbi decoder which conducts forward error correcting decoding. A synchronization detecting circuit which detects the synchronization of codes is connected to the Viterbi decoder; the block phase control circuit is controlled on the basis of the results of the code synchronization detection.
In the transmitter, the interleaver circuit sequentially writes digital signals, converted into forward error correction codes by the convolution encoder in the row direction, into memories which are arranged, for example so as to consist of seven memories in the row direction and four in the column direction and then, the interleaver circuit sequentially reads out data written into the memories in the column direction (see FIG. 8). The read-out data are modulated by the digital modulator, and transmitted to the transmission line.
Then, in the receiver, the transmitted digital modulated signal is demodulated by the digital demodulator and is input to the block phase control circuit. When a code is determined not to be in synchronization with a certain integral period in the synchronization detecting circuit, the block phase control circuit causes a shift for one symbol of the partition of deinterleaved block. This shift is continued until code synchronization is confirmed, and upon determination of synchronization, then block partition is kept. This utilizes the fact that disagreement between the block partition interleaved on the transmission side and the block partition to be deinterleaved on the receiving side makes it impossible to achieve synchronization of the Viterbi decoder.
Thus, an interleaved block partition is found on the receiving side using the synchronization detecting circuit, so as to cause deinterleaving for each block partition, and forward error correcting decoding is accomplished by the Veterbi decoder (for example, see Japanese Laid-Open Patent Publication No. 3-32, 131; for code synchronization, see, for example: Yasuda et al. "Code Synchronizing Method in Viterbi Decoding," The Transaction of the Institute of the Electronics Information and Communication Engineers, (B), vol. J66-B, No. 5, pp. 623-630 (May 1983)).
In the configuration as described above, however, data columns before interleaving remain at many points even when interleaving has been accomplished at a wrong block partition as shown in FIG. 8, and another problem is the possibility of erroneous synchronization detection in the synchronization detecting circuit.